1. Field of the Invention
The present invention relates to digital circuits; and more particularly, to a pulse width modifying digital circuit generated by a digital state machine.
2. Description of Related Art
Many applications will show an improvement in performance or allow a more straightforward and cost-effective implementation if certain pulse signals with selectively variable pulse widths are employed. These pulse widths should deviate from the standard clock pulse width, as desired. However, Applicant is not aware of any such feasible circuit design. As a result, designers either focus on improving other aspects of these applications to improve performance or tolerate existing problems.
One such application is Row Access Strobe (RAS) and Column Access Strobe (GAS) generation in Dynamic Random Access Memory (DRAM) systems. This system requires a pulse that is slightly longer than the time between any two adjacent edges of the clock signal. In particular, transferring data to and from a Page Mode DRAM every 40 nanosecond (ns) is possible, but typically, devices require a GAS signal with a 25 ns active time and a 15 ns inactive time. Using a digital clock signal with a 40 ns period, a circuit that generates a 20 ns active time and a 20 ns inactive time is readily realizable. However, a circuit that generates a 25 ns/15 ns signal is not known or available using strictly digital integrated circuit technology.
One approach to satisfying device requirements of a 25 ns active time and 15 ns inactive time CAS signal is to generate a 25 ns/25 ns signal. However, this signal limits the data transfer speed to 50 ns per data item transfer, which is much slower than the 40 ns which the device will support. Another approach is to utilize an analog-based off-chip discrete tuned delay line, such as an inductor-capacitor tuned resonant circuit. These analog-based tuned circuits are not readily implementable on the same IC gate array chip and generally adds cost to the design. In addition, using analog components is not very stable or reliable for generating short delays, such as 25 ns; analog components are susceptible to temperature and voltage variances. Thus, an analog circuit designed to provide 25 ns may actually provide a wide range of delays, from 15 to 40 ns. Furthermore, some analog designs increase signal skew in the process of stretching the pulse width from 20 to 25 ns. Still other approaches provide internal pulse generators that provide a pulse that is smaller than the clock period. But this approach adds complexity to the design.
Another application that benefits from a variable pulse width generating digital circuit is a tri-state output enable signal generation circuit for use with high speed buses. High speed buses having lines which allow multiple users to drive the line can be termed bi-directional. Several problems are encountered when standard tri-statable CMOS drivers are used to drive bi-directional lines on such buses. One significant problem is caused by imperfect synchronization of the multiple drivers attached to the bus. If there is any overlap between the time one driver is turned off and another driver is turned on, there may be a very large current running between them. The effect of this contention for control of the state of the bus line is described with reference to FIG. 2 below.
The typical method used to eliminate the current spike is to put an off cycle between the times when the signals are driven by different drivers. Unfortunately, this method results in lost cycles. Lost cycles can be particularly painful when there are a lot of small burst transfers from random channels on the bus.
Another way in which the current spike can be reduced is by going with open drain outputs which are tied together and attached to a pull up resistor. In this situation, there is less problem with a change in current since the current is about the same whether one device or two devices are driving the line. The downside of this method is that the only way for a signal to rise is through the pull up resistor. This creates a troublesome tradeoff for high speed buses. That is, small resistors are required to achieve fast rise times. However, small resistors result in an increase in DC current.
Accordingly, it is desirable to provide a high speed, tri-state bus having bi-directional lines which do not suffer the cycle time delay or high current device contention of prior art designs during bus reversal. Additionally, a digital circuit that generates a pulse with a variable pulse width is particularly desirable for DRAM systems employing RAS/CAS signals. CAS signals generated by a digital state machine and providing a non-constant, or variable, pulse width signal is particularly advantageous for those devices with specific CAS signal requirements for data transfer. In sum, a need exists in the industry for a circuit that provides a variabte pulse width signal that can be generated by a digital state machine which is cost-effective and relatively simple in implementation.